FIG. 6 is a circuit diagram showing an example of a differential amplifier circuit according to a prior art. In FIG. 6, reference numeral 1 indicates a signal source in which an ac voltage signal is superimposed on a dc voltage source, and signals on two terminals are respectively inputted to bases of NPN transistors Q1 and Q2 forming a differential input section 2. Further, collectors of the NPN transistors Q1 and Q2 are respectively connected to a first voltage source Vcc through resistors R1 and R2, and emitters are respectively connected to a second voltage source Vee through constant current sources I4 and I5. Furthermore, the emitters of the NPN transistors Q1 and Q2 are connected to each other through a capacitor C5.
Referring to FIG. 6, as a specific example of the signal source 1 in which an ac voltage signal is superimposed on a dc voltage source, a magneto-resistive head (MRH) is known.
In the operation of this conventional differential amplifier circuit, between ac voltage component and dc voltage component on the two terminals of the signal source 1, influence of the dc voltage component is removed by the capacitor C5. And a signal formed by amplifying only the ac voltage component from the collectors of the transistors Q1 and Q2 is outputted from an output terminal.
In the arrangement shown in FIG. 6, supposing that the constant current sources I4 and I5 are respectively 5 mA, it is calculated that to get a lower limit cutoff frequency of 1 MHz in the amplifier circuit, a value of the capacitor C5 mounting to 0.0156 .mu.F. is required.
This value of 0.0156 .mu.F. of the capacitor C5 is a so large value that it is difficult to incorporate any ordinary capacitor in a semiconductor integrated circuit. Thus, there is a disadvantage that such a capacitor is obliged to be disposed from outside in the form of an outside part.
To overcome such a disadvantage, as shown in FIG. 7, there has been provided an improved differential amplifier circuit capable of incorporating a capacitor in the semiconductor integrated circuit.
In FIG. 7, two terminals of the signal source 1 are respectively connected to bases of NPN transistors Q13 and Q14. Collectors of the NPN transistors Q13 and Q14 are respectively connected to a first power source Vcc, and their emitters are respectively connected to a second voltage source Vee through constant current sources I6 and I7.
Further, the emitters of the NPN transistors Q13 and Q14 are connected to bases of NPN transistors Q1 and Q2 forming a differential input section through capacitors C6 and C7. Further, collectors of the NPN transistors Q1 and Q2 are respectively connected to the first voltage source Vcc through resistors R11 and R2, and respectively connected to output terminals. Furthermore, emitters of the NPN transistors Q1 and Q2 are connected to each other, and connected to the second voltage source Vee through a constant current source I1.
In the above differential amplifier circuit comprising the NPN transistors Q1 and Q2, between ac voltage component and dc voltage component on the two terminals of the signal source 1, only the ac voltage component is inputted by the capacitors C6 and C7, and therefore an operation for amplifying only the ac voltage component is performed.
In the arrangement shown in FIG. 7, supposing that the constant current source I1 is 10 mA, it is calculated that to get a lower limit cutoff frequency of 1 MHz in the amplifier circuit, values of the capacitors C6 and C7 respectively mounting to 153 pF are required.
This value of the capacitors is a large value of a level making it possible to incorporate the capacitors in a semiconductor integrated circuit.
However, when the capacitors C6 and C7 are incorporated in the semiconductor integrated circuit, to prevent the two terminals of the signal source 1 from being influenced by parasitic capacity component of the capacitors C6 and C7, it is essential to provide the NPN transistors Q13 and Q14 therebetween. Hence there arises a further problem that to reduce noise generated in the NPN transistors Q13 and Q14, a collector current applied to the NPN transistors Q13 and Q14 must be equivalent to that applied to the NPN transistors Q1 and Q2 forming the differential amplifier circuit. In other words, to form a circuit of less noise, a problem exists in that a collector current not less than 5 mA is required for each of the NPN transistor Q1, Q2, Q13 and Q14, which results in considerable power consumption in the entire circuit.
Thus, in the conventional differential amplifier circuit arranged as mentioned above, there exists a problem that it is impossible to incorporate any capacitor in the semiconductor integrated circuit or that even if it is possible to incorporate it, large power consumption is unavoidable.